In semiconductor technology, an integrated circuit can be formed on a semiconductor substrate according to a particular technology node, which typically indicates a minimum feature size. When the minimum feature size moves to about 100 nm or below, damascene processes are frequently utilized to form multilayer copper interconnections including vertical interconnection vias and horizontal interconnection metal lines. As semiconductor device sizes continue to shrink, the damascene process will see a number of potential problems that may affect the quality of the interconnections. For example, in a 20-nanometer (nm) fabrication process, the openings may become too narrow and thus may not be properly filled by conventional damascene processes. The top portion of the opening may be blocked, which may create a void underneath that may degrade the performance of the semiconductor device. This problem is particularly acute in high aspect ratio features of small width.